In the past, the integrity of transmission paths has usually been verified using a signature test. A signature comprised of a predetermined pattern of data bits is transmitted through a transmission path under test and is compared to the data received at a receiver. The transmission path under test is considered to be fault-free if the received data matches the transmitted data.
More recently, transmission circuits have become increasingly more complex with a requirement for data to be transmitted at higher rates. As bit rates increase, the need for the testing of transmission circuits becomes more essential since a transmission circuit which performs adequately at low frequencies may not perform adequately at much higher frequencies and may cause data to become corrupt. Transmission circuits capable of transmitting data at high frequencies often have many closely inter-spaced data lines forming a data bus. It is not uncommon for noise to be generated on the bus as data bits carried on the data bus are changing binary values at very high frequencies. This noise is often the cause of data corruption, resulting in the loss of integrity of a transmitted data message. A static data test such as a signature test may not detect data corruption in a circuit capable of transmitting large amounts of data at very high frequencies. Thus, it is desirable to provide test data which is random or pseudo random and which covers a myriad of possible bit combinations thereby to provide varying stimuli for a transmission circuit under test. Pseudo random data is comprised of many varying patterns which, while appearing random, are periodically based.
In the past, large memory devices have been used to store test data; however, memory devices capable of storing an adequate amount of test data are physically large and may not be practically incorporated on an integrated circuit that also includes the circuit under test.
It is therefore an object of the invention to provide an improved method and circuit for testing the integrity of a transmission path.
It is also an object of the invention to provide testing circuitry that may be co-located on an integrated circuit also containing at least a portion of the circuit to be tested.
It is a further object of the invention to provide testing circuitry that is adapted to exercise the circuit under test at a data rate similar to that normally sent through the circuit under test.